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this is information on a product in full production. august 2012 doc id 022335 rev 3 1/24 1 stm6524 6-pin smart reset? datasheet ? production data features operating voltage 1.65 v to 5.5 v low supply current 1.5 a integrated test mode dual smart reset? push-button inputs with fixed extended reset setup delay (t src ) from 0.5 s to 10 s in 0.5 s steps (typ.), option with internal pull-up resistor push-button controlled reset pulse duration ? option 1: fully push-button controlled, no fixed or minimum pulse width guaranteed ? option 2: defined output reset pulse duration (t rec ), factory-programmed no power-on reset single reset output ? active low or active high ? push-pull or open drain with optional pull- up resistor fixed smart reset? input logic voltage levels operating temperature: ?40 c to +85 c udfn6 package: 1.6 mm x 1.3 mm ecopack ? 2 (rohs compliant, halogen- free) applications mobile phones, smartphones, pdas e-books mp3 players games portable navigation devices any application that requires delayed reset push-button(s) response for improved system stability. udfn6 1.6 mm x 1.3 mm www.st.com
contents stm6524 2/24 doc id 022335 rev 3 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 power supply (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 ground (v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 smart reset? input (sr0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 smart reset? input (sr1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 reset output (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10 package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
stm6524 list of tables doc id 022335 rev 3 3/24 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. dc and ac characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. mechanical data for udfn6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch . . . . . . . . . . . . . . . . . . . 19 table 6. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
list of figures stm6524 4/24 doc id 022335 rev 3 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. single-button smart reset? typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. dual-button smart reset? typical hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. option without t rec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. option with t rec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. undervoltage condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. supply current (i cc ) vs. temperature (t a ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. smart reset? delay (t src ) vs. temperature (t a ), t src = 7.5 s (typ.). . . . . . . . . . . . . . . . . 13 figure 11. test mode entry voltage (v test ) vs. temperature (t a ). . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 12. initial test mode time (t src-ini ) vs. temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 13. package outline for udfn6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch . . . . . . . . . . . . . . . . . . . . 18 figure 14. footprint recommendation for udfn6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch. . . . . . . . . . . . 19 figure 15. carrier tape for udfn6 1.6 x 1.3 x 0.55 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 16. pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17. package marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
stm6524 description doc id 022335 rev 3 5/24 1 description the smart reset? devices provide a useful feature that ensures inadvertent short reset push-button closures do not cause system resets. this is done by implementing extended smart reset? input delay time (t src ) and combined push-button inputs, which together ensures a safe reset and eliminates the need for a specific dedicated reset button. this reset configuration provides versatility and allows the application to distinguish between a software generated interrupt and a hard system reset. when the input push-buttons are connected to microcontroller interrupt inputs, and are closed for a short time, the processor can only be interrupted. if the system still does not respond pro perly, continuing to keep the push-buttons closed for the extended setup time t src causes a hard reset of the processor through the reset output. the stm6524 has two combined delayed smart reset? inputs (sr0 , sr1 ) with preset delayed smart reset? setup time (t src ). the reset output is asserted after both of the smart reset? inputs were held active for the selected t src delay time. depending on selected option the rst output remains asserted either until at least one sr input goes to inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset pulse duration is fixed for t rec (i.e. factory-programmed). the reset output, rst , is active low or active high, push-pull or open drain with optional pull-up resistor. the device fully operates over a broad v cc range 1.65 v to 5.5 v. below 1.575 v typ. the inputs are ignored and outputs are deasserted; the deasserted reset output levels are then valid down to 1.0 v. test mode after pull of sr0 up to v test or more (v cc + 1.4 v, max.) we start counting initial shorten t src-ini (42 ms, typ.). after t src-ini expires, the rst output either goes down for t rec (if t rec option is used) or stays low as long as overvoltage on sr0 in detected (if t rec option is not used). this is a feedback and a user knows that the device is locked in the test mode. each time both sr inputs are connected to ground in test mode a shorten t src-short (21 ms, typ.) is used instead of long t src (0.5 s -10 s). return from to normal mode is possible by a new startup of the device (i.e. v cc goes to 0 v and back to its original state). in this way the device can be quickly tested without repeating test mode triggering. advantage of this solution is pretty high glitch immunity, feedback to user about entry to the test mode and testability within full v cc range.
description stm6524 6/24 doc id 022335 rev 3 figure 1. logic diagram figure 2. pin connections (top view) 34- 234 '.$ 6 ## 32 32 !- 34- 6 33 .# 6 ## 32 234 32 !-
stm6524 description doc id 022335 rev 3 7/24 figure 3. block diagram table 1. signal names pin name type description 1 v ss supply ground ground 2 sr1 input secondary push-button smart reset? input. active low. optional pull-up resistor. 3 rst output reset output (open drain with optional pull-up resistor, active low) (push-pull ? active low or active high) 4 nc - not connected (not bonded; should be connected to v ss ) 5 sr0 input primary push-button smart reset? input. active low. optional pull-up resistor. 6 v cc supply voltage positive supply voltage for the device. a 0.1 f decoupling ceramic capacitor is recommended to be connected between v cc and v ss pins, as close to the stm6524 device as possible. t 32# generator t 2%# generator optional 234 !.$ /vervoltagedetect testmodetrigger 32 32 !-6
pin descriptions stm6524 8/24 doc id 022335 rev 3 2 pin descriptions 2.1 power supply (v cc ) this pin is used to provide power to the smart reset? device. a 0.1 f ceramic decoupling capacitor is recommended to be connected between the v cc and v ss pins, as close to the stm6524 device as possible. 2.2 ground (v ss ) ground pin for the device. 2.3 smart reset? input (sr0 ) push-button smart reset? input is active low with optional pull-up resistor. both sr inputs need to be asserted simultaneously for at least t src to assert the reset output (rst ). by connecting a voltage higher than v cc to the sr0 the device enters a test mode (see section 1: description on page 5 for more information). 2.4 smart reset? input (sr1 ) push-button smart reset? input is active low with optional pull-up resistor. both sr inputs need to be asserted simultaneously for at least t src to assert the reset output (rst ). 2.5 reset output (rst ) rst is active low or active high, push-pull or open drain reset output with optional internal pull-up resistor. output reset pulse width is optional as follows: neither fixed nor minimum output reset pulse duration (releasing the push-button while reset output is active, causes the output to de-assert); fixed, factory-programmed output reset pulse duration for t rec independent on smart reset? input state. if v cc drops below 1.575 v, the rst output is deasserted and its state is guaranteed down to 1 v (see figure 8 ).
stm6524 typical application diagram doc id 022335 rev 3 9/24 3 typical application diagram figure 4. single-button smart reset? typical hookup 1. external pull-up resistor requested if the reset output (rst ) is open drain type without internal pull-up. 2. external pull-up resistor requested if the smart reset? inputs (sr0 and sr1 ) have no internal pull-up. 3. when only one smart reset? input push-button is used, tie both the sr inputs together. 6 ## 6 ## 6 ## 053( "544/. 37)4#( -#5 234 6 33 6 33 32 32 34- 2%3%4 ).4 .-) !-6
typical application diagram stm6524 10/24 doc id 022335 rev 3 figure 5. dual-button smart reset? typical hookup 1. external pull-up resistor requested if the reset output (rst ) is open drain type without internal pull-up. 2. external pull-up resistor requested if the smart reset? inputs (sr0 and sr1 ) have no internal pull-up. 6 ## 6 ## 6 ## 053( "544/. 37)4#( 053( "544/. 37)4#( -#5 234 6 33 6 33 32 32 34- 2%3%4 ).4 .-) !-6
stm6524 timing waveforms doc id 022335 rev 3 11/24 4 timing waveforms figure 6. option without t rec figure 7. option with t rec 6 ## 32 234 32 6 6 'litch immunity t 32# !-6 6 6 3tart timer %nd timer 0ush button controlledoutput !-6 234 'litch immunity 6 ## 6 6 32 t 32# t 2%# 32 6 6
timing waveforms stm6524 12/24 doc id 022335 rev 3 figure 8. undervoltage condition 1. if undervoltage occurs (v cc drops below 1.575 v typ.) while reset output is active, the reset output is released and goes inactive. !- 6 ## 32 234 32 6 6 6 6 6 6 6 6 6 t 32# 4imes
stm6524 typical operating characteristics doc id 022335 rev 3 13/24 5 typical operating characteristics figure 9. supply current (i cc ) vs. temperature (t a ) figure 10. smart reset? delay (t src ) vs. temperature (t a ), t src = 7.5 s (typ.) 4emperature?# 3upplycurrent) ## ?! 6 ## 6 6 ## 6 6 ## 6 !-6 4emperature?# 3mart2eset 4- delayt 32 # s 6 ## 6 6 ## 6 6 ## 6 !-6
typical operating characteristics stm6524 14/24 doc id 022335 rev 3 figure 11. test mode entry voltage (v test ) vs. temperature (t a ) figure 12. initial test mode time (t src-ini ) vs. temperature (t a ) !- 4emperature4 ! ?# 4estmodeentryvoltage6 4%34 6 6 ## 6 6 ## 6 6 ## 6 !- 4emperature4 ! ?# )nitialtestmodetimet 32 #?).) ms 6 ## 6 6 ## 6 6 ## 6
stm6524 maximum ratings doc id 022335 rev 3 15/24 6 maximum ratings stressing the device above the rating listed in table 2: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in table 3: operating and measurement conditions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics? sure program and other relevant quality documents. table 2. absolute maximum ratings symbol parameter value unit t stg storage temperature (v cc off) -55 to +150 c t sld (1) 1. reflow at peak temperature of 260 c. the time above 255 c must not exceed 30 seconds. lead solder temperature for 10 seconds 260 c v io input or output voltage -0.3 to 5.5 (2) 2. for push-pull rst output type only from -0.3 v to v cc +0.3 v. v v cc supply voltage -0.3 to 7 v esd v hbm electrostatic discharge protection, human body model (jesd22- a114-b level 2) 2kv v rcdm electrostatic discharge protection, charged device model, all pins 1 kv v mm electrostatic discharge protection, machine model, all pins (jesd22-a115-a level a) 200 v latch-up (v cc pin, sr0 reset input pin) eia/jesd78 -
dc and ac parameters stm6524 16/24 doc id 022335 rev 3 7 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in table 4: dc and ac characteristic that follow, are derived from tests performed under the measurement conditions summarized in table 3: operating and measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 3. operating and measurement conditions symbol parameter value unit v cc supply voltage 1.65 to 5.5 v t a ambient operating temperature -40 to +85 c
stm6524 dc and ac parameters doc id 022335 rev 3 17/24 table 4. dc and ac characteristic symbol parameter test conditions (1) 1. valid for ambient operating temperature t a = -40 to +85 c, v cc = 1.65 to 5.5 v. min. typ. (2) 2. typical values are at 25 c and v cc = 3.3 v unless otherwise noted. max. unit v cc supply voltage (3) 3. reset outputs are deasserted below 1.575 v typ. and remain deasserted down to v cc = 1 v. 1.65 5.5 v i cc supply current (inputs in their inactive state, t src counter is not running) v cc = 3.0 v 1.1 2.5 a v cc = 5.0 v 1.5 3.0 a v ol reset output voltage low v cc 4.5 v, sinking 3.2 ma 0.3 v v cc 3.3 v, sinking 2.5 ma 0.3 v v cc 1.65 v, sinking 1 ma 0.3 v v oh reset output voltage high (push-pull output only) v cc 4.5 v, i source = 0.8 ma 0.8 v cc v v cc 2.7 v, i source = 0.5 ma 0.8 v cc v v cc 1.65 v, i source = 0.25 ma 0.8 v cc v t rec reset timeout delay, factory-programmed (device option) 0.85 1.28 1.71 ms 66 100 134 ms 140 210 280 ms 240 360 480 ms r puo internal output pull-up resistor on rst (device option) 65 k i lo output leakage current v rst = 5.5 v, open drain device option without output pull-up resistor -0.1 0.1 a smart reset tm t src smart reset? delay t a = -40 to +85 c 0.8 x t src t src (4) 4. factory-programmable in the range of 0.5 s to 10 s typ. in 0.5 s steps (see table 7 for available delays). 1.2 x t src s t a = 25 c 0.9 x t src 1.1 x t src v il sr0 , sr1 input voltage low v ss -0.3 0.3 v v ih sr0 , sr1 input voltage high 0.85 5.5 v i li sr0 , sr1 input leakage current -0.1 0.1 a input glitch immunity (5) 5. input glitch immunity is equal to t src , when both inputs (sr0 and sr1 ) are low. otherwise infinite. sr0 and sr1 asserted t src s test mode v test test mode entry voltage v cc +0.9 v cc +1.1 v cc +1.4 v t src-ini initial test mode time 28 42 56 ms t src- short shorten smart reset? delay 16.8 21 25.2 ms
package information stm6524 18/24 doc id 022335 rev 3 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 13. package outline for udfn6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch % # # 0).).$%8!2%! $x% ! # x ,x "/44/-6)%7 bx 3)$%6)%7 e # 4/06)%7 x ! # ! " # 3%!4). ' 0,!. % # 0).).$%8!2%! $x% $ x " ! !-
stm6524 package information doc id 022335 rev 3 19/24 table 5. mechanical data for udfn6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch figure 14. footprint recommendation for udfn6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch symbol dimensions note drawing (millimeters) drawing (inches) min. typ. max. min. typ. max. a 0.50 0.55 0.60 0.020 0.022 0.024 a1 0.00 0.02 0.05 0.0000 0.0008 0.0020 b 0.15 0.20 0.25 0.006 0.008 0.010 d 1.30 bsc 0.051 bsc e 1.60 bsc 0.063 bsc e 0.40 bsc 0.016 bsc l 0.250 0.325 0.400 0.0098 0.0128 0.0157 n6 6 !-
package information stm6524 20/24 doc id 022335 rev 3 figure 15. carrier tape for udfn6 1.6 x 1.3 x 0.55 mm 1. measured from centreline of sprocket hole to centreline of pocket. 2. cumulative tolerance of 10 sprocket holes is 0.20. 3. measured from centreline of sprocket hole to centreline of pocket. 4. other material available. 5. typical sr of formed tape max. 10 9 / sq. 6. all dimensions in millimeters unless otherwise stated. figure 16. pin 1 orientation !- 7 0o 0 & % ? !o 4 ? +o # , 3%#4)/.9 9 2%& ? "o !o ? "o ? +o ? & ? 0 ? 7 ? ? 0 ? 9 9 $ ?? !- 5serdirectionoffeed
stm6524 part numbering doc id 022335 rev 3 21/24 9 part numbering table 6. ordering information scheme example: stm6524 a h a r dl 6 f device type stm6524 reset (v cc monitoring threshold) voltage v rst a = no v cc monitoring feature smart reset? set up delay (t src ) (1) 1. smart reset tm delay (t src ) is available from 0.5 s to 10 s in 0.5 s steps (typ.). minimum order quantities may apply. contact local sales office for availability. h = factory programmable t src = 4.0 s, no pull-up l = factory programmable t src = 6.0 s, no pull-up p = factory programmable t src = 7.5 s, no pull-up u = factory programmable t src = 10.0 s, no pull-up outputs type a = open drain, no pull-up, active low c = open drain, 50 k internal pull-up resistor, active low d = push-pull, active low h = push-pull, active high reset timeout period (t rec ) a = factory programmable t rec = 210 ms (typ.) b = factory programmable t rec = 360 ms (typ.) e = factory programmable t rec = 1.28 ms (typ.) f = factory programmable t rec = 100 ms (typ.) r = push-button controlled package dl = udfn6 temperature range 6 = -40 c to +85 c shipping method f = tape and reel
package marking information stm6524 22/24 doc id 022335 rev 3 10 package marking information figure 17. package marking (top view) table 7. package marking part number t src (s) smart reset? inputs (1) 1. al = active low. output type (2) 2. od = open drain, al = active low. t rec option (ms) (3) 3. no t rec = push-button controlled reset pulse width. package topmark stm6524ahardl6f 4.0 al od, al no t rec udfn6 ha STM6524ALABDL6F 6.0 al od, al 360 udfn6 lc stm6524alardl6f 6.0 al od, al no t rec udfn6 la stm6524apardl6f 7.5 al od, al no t rec udfn6 pa stm6524auabdl6f 10.0 al od, al 360 udfn6 uc stm6524auardl6f 10.0 al od, al no t rec udfn6 ua ! " !- !dotpinreference "markingareatopmark
stm6524 revision history doc id 022335 rev 3 23/24 11 revision history table 8. document revision history date revision changes 07-oct-2011 1 initial release. 13-jun-2012 2 updated features , section : test mode , ta ble 4 , title of section 8 , minor text corrections throughout document. 31-aug-2012 3 updated ta b l e 7 (added ?(ms)? to t rec option, added STM6524ALABDL6F and stm6524auabdl6f devices).
stm6524 24/24 doc id 022335 rev 3 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at an y time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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